AMDGPU: Created a subclass for the return address operand in the tail call return...
authorChangpeng Fang <changpeng.fang@amd.com>
Thu, 30 Mar 2023 18:13:21 +0000 (11:13 -0700)
committerChangpeng Fang <changpeng.fang@amd.com>
Thu, 30 Mar 2023 18:13:21 +0000 (11:13 -0700)
commit7a98934fadc3581ff024a77dc696b62f1a538ad5
tree83fd369d0407e944d98f2eb9a7085becb35c97b2
parent6a08c2be5880cdaee01031b55c79126ec3d688e2
AMDGPU: Created a subclass for the return address operand in the tail call return instruction

Summary:
  This is to avoid using the callee saved registers for the return address of the tail call return instruction.

Reviewers:
  arsenm, cdevadas

Differential Revision:
  https://reviews.llvm.org/D147096
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll