mmc: sh-mmcif: properly handle MMC_WRITE_MULTIPLE_BLOCK completion IRQ
authorGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Tue, 18 Sep 2012 23:10:24 +0000 (23:10 +0000)
committerChris Ball <cjb@laptop.org>
Wed, 3 Oct 2012 14:05:27 +0000 (10:05 -0400)
commit7a7eb3286b8e078d6f5de56a2e26a3bb248085eb
treebe668aee14461db0c4ba60c231dc5cb7314beea4
parent387a8cbdf84d5c417d24eabfdf9fe4e0b94458da
mmc: sh-mmcif: properly handle MMC_WRITE_MULTIPLE_BLOCK completion IRQ

Upon completion of a MMC_WRITE_MULTIPLE_BLOCK command MMCIF issues an IRQ
with the DTRANE bit set and often with one or several of CMD12 bits set.
If those interrupts are not acknowledged, an additional interrupt can be
produced and will be delivered later, possibly, when the transaction has
already been completed. To prevent this from happening, CMD12 completion
interrupt sources have to be cleared too upon reception of an DTRANE IRQ.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Tested-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Chris Ball <cjb@laptop.org>
drivers/mmc/host/sh_mmcif.c