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[PowerPC] Implement P10 Byte Reverse Insructions
authorLei Huang <lei@ca.ibm.com>
Tue, 20 Dec 2022 16:11:55 +0000 (10:11 -0600)
committerLei Huang <lei@ca.ibm.com>
Wed, 21 Dec 2022 15:15:57 +0000 (09:15 -0600)
commit7a7e9109a2d64a1c09b5dbe958893329fc30467e
treeb9853ba0590bdb017fb92ddef8232e2c73b38c1etree | snapshot
parent3e65ad7482e9e612abcc115f8fb2ed379fcad612commit | diff
[PowerPC] Implement P10 Byte Reverse Insructions

Generate brh, brw and brd instructions for byte-swap operations
on P10 and generating a single instruction for a 32-bit swap followed
by a 16-bit right shift.

Reviewed By: stefanp

Differential Revision: https://reviews.llvm.org/D140414
llvm/lib/Target/PowerPC/P10InstrResources.td diff | blob | history
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp diff | blob | history
llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff | blob | history
llvm/lib/Target/PowerPC/PPCInstrP10.td diff | blob | history
llvm/test/CodeGen/PowerPC/p10-bswap.ll [new file with mode: 0644] blob
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt diff | blob | history
llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s diff | blob | history
Domain: System / Toolchain;