clk: sunxi: Add driver for A80 MMC config clocks/resets
authorChen-Yu Tsai <wens@csie.org>
Tue, 20 Jan 2015 15:46:31 +0000 (23:46 +0800)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Tue, 20 Jan 2015 16:14:38 +0000 (17:14 +0100)
commit7a6fca879f59824963cd456d8cc5db24ac5acfc0
treec9519f6cb366fe1c3a3545c55f89e664f88e6a54
parent61af4d8dceeb179b62cb342f4008ce3774d3d1fd
clk: sunxi: Add driver for A80 MMC config clocks/resets

On the A80 SoC, the 4 mmc controllers each have a separate register
controlling their register access clocks and reset controls. These
registers in turn share a ahb clock gate and reset control.

This patch adds a platform device driver for these controls. It
requires both clocks and reset controls to be available, so using
CLK_OF_DECLARE might not be the best way.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Documentation/devicetree/bindings/clock/sunxi.txt
drivers/clk/sunxi/Makefile
drivers/clk/sunxi/clk-sun9i-mmc.c [new file with mode: 0644]