vsx.md (peephole for optimizing move SF to GPR): Adjust code to eliminate needing...

vsx.md (peephole for optimizing move SF to GPR): Adjust code to eliminate needing to do the shift right 32-bits operation after...

[gcc]
2017-09-26  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/vsx.md (peephole for optimizing move SF to GPR):
	Adjust code to eliminate needing to do the shift right 32-bits
	operation after XSCVDPSPN.

[gcc/testsuite]
2017-09-26  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/pr71977-1.c: Update test to know that we
	don't generate a 32-bit shift after doing XSCVDPSPN.
	* gcc.target/powerpc/direct-move-float1.c: Likewise.
	* gcc.target/powerpc/direct-move-float3.c: New test.

From-SVN: r253223