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author	Craig Topper <craig.topper@sifive.com>
	Thu, 20 Jan 2022 19:49:35 +0000 (11:49 -0800)
committer	Craig Topper <craig.topper@sifive.com>
	Thu, 20 Jan 2022 20:40:07 +0000 (12:40 -0800)
commit	7a275dc35411b8c3f510166f40c225cd10dc5eec
tree	04090063c18ed1b1d0fac71ca2f74d9001fd3cab	tree \| snapshot
parent	e99835ffedc23cc132c8a9c769c85ac20b66cb3a	commit \| diff

[RISCV] Remove Zvlsseg extension.

This string no longer appears in the Vector Extension specification.
The segment load/store instructions are just part of the vector
instruction set.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D117724

33 files changed:

clang/include/clang/Basic/RISCVVTypes.def		diff \| blob \| history
clang/include/clang/Basic/riscv_vector.td		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c		diff \| blob \| history
clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c		diff \| blob \| history
clang/test/Driver/riscv-arch.c		diff \| blob \| history
clang/test/Preprocessor/riscv-target-features.c		diff \| blob \| history
clang/utils/TableGen/RISCVVEmitter.cpp		diff \| blob \| history
llvm/lib/Support/RISCVISAInfo.cpp		diff \| blob \| history
llvm/lib/Target/RISCV/RISCV.td		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVInstrInfoV.td		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVSchedRocket.td		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVSubtarget.h		diff \| blob \| history
llvm/test/CodeGen/RISCV/attributes.ll		diff \| blob \| history
llvm/test/MC/RISCV/attribute-arch-invalid.s		diff \| blob \| history
llvm/test/MC/RISCV/attribute-arch.s		diff \| blob \| history
llvm/test/MC/RISCV/rvv/zvlsseg.s		diff \| blob \| history

Domain: System / Toolchain;

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