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author	Matthias Braun <matze@braunis.de>
	Wed, 24 Aug 2016 01:32:41 +0000 (01:32 +0000)
committer	Matthias Braun <matze@braunis.de>
	Wed, 24 Aug 2016 01:32:41 +0000 (01:32 +0000)
commit	79f85b3b8ff8e54e9c94870477f2868929e481b7
tree	67b36c04f6c3f2f4f73e0361a42cf993bb619d41	tree \| snapshot
parent	b31163136ca249127b95a457308c7de3cb7a9841	commit \| diff

MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.

Specifying isSSA is an extra line at best and results in invalid MI at
worst. Compute the value instead.

Differential Revision: http://reviews.llvm.org/D22722

llvm-svn: 279600

70 files changed:

llvm/include/llvm/CodeGen/MIRYamlMapping.h		diff \| blob \| history
llvm/lib/CodeGen/MIRParser/MIRParser.cpp		diff \| blob \| history
llvm/lib/CodeGen/MIRPrinter.cpp		diff \| blob \| history
llvm/lib/CodeGen/MachineVerifier.cpp		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/legalize-property.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/GlobalISel/verify-selected.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir		diff \| blob \| history
llvm/test/CodeGen/AArch64/movimm-wzr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/AArch64/machine-scheduler.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/Generic/frame-info.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/Generic/register-info.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/function-liveins.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/generic-instr-type.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/metadata-operands.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/stack-object-operands.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/standalone-register-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/subregister-operands.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/undefined-register-class.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir		diff \| blob \| history
llvm/test/CodeGen/MIR/X86/virtual-registers.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir		diff \| blob \| history
llvm/test/CodeGen/X86/eflags-copy-expansion.mir		diff \| blob \| history
llvm/test/CodeGen/X86/fixup-bw-copy.mir		diff \| blob \| history
llvm/test/CodeGen/X86/implicit-null-checks.mir		diff \| blob \| history
llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir		diff \| blob \| history
llvm/test/DebugInfo/MIR/X86/live-debug-values.mir		diff \| blob \| history

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