AMDGPU/SI: Add back reverted SGPR spilling code, but disable it
authorMarek Olsak <marek.olsak@amd.com>
Fri, 25 Nov 2016 17:37:09 +0000 (17:37 +0000)
committerMarek Olsak <marek.olsak@amd.com>
Fri, 25 Nov 2016 17:37:09 +0000 (17:37 +0000)
commit79c05871a28872a01e5e75394c5c6382d5c434a5
tree29ee3868682c95cf84a8912c3c911d6948f17d37
parentc5fb167df05538ad6cd0b4e967187bf0bac44f19
AMDGPU/SI: Add back reverted SGPR spilling code, but disable it

suggested as a better solution by Matt

llvm-svn: 287942
21 files changed:
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInsertWaits.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.h
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
llvm/test/CodeGen/AMDGPU/basic-branch.ll
llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir
llvm/test/CodeGen/AMDGPU/inline-constraints.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll
llvm/test/CodeGen/AMDGPU/read_register.ll
llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
llvm/test/CodeGen/AMDGPU/spill-m0.ll
llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
llvm/test/CodeGen/MIR/AMDGPU/scalar-store-cache-flush.mir [new file with mode: 0644]
llvm/test/CodeGen/MIR/AMDGPU/si-fix-sgpr-copies.mir