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clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider
authorChen-Yu Tsai <wens@csie.org>
Wed, 26 Nov 2014 07:16:52 +0000 (15:16 +0800)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Sun, 21 Dec 2014 22:51:37 +0000 (23:51 +0100)
commit7954dfaee386d45d6ec655e5153ad67edf311a56
treec8ebbdba5b2e9d16782133b2e8ca3e0db683a87atree | snapshot
parent75bd2ec1a65a30094f630f9c5bf3ecfe9549496fcommit | diff
clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider

This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the pre-divider on the PLL6 input, thus allowing the clock to
be muxed to PLL6 with proper clock rate calculation.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Documentation/devicetree/bindings/clock/sunxi.txt diff | blob | history
drivers/clk/sunxi/clk-sunxi.c diff | blob | history
Domain: System / Kernel;