clk: pistachio: Fix PLL rate calculation in integer mode
authorZdenko Pulitika <zdenko.pulitika@imgtec.com>
Wed, 26 Aug 2015 16:11:39 +0000 (17:11 +0100)
committerStephen Boyd <sboyd@codeaurora.org>
Wed, 26 Aug 2015 18:34:41 +0000 (11:34 -0700)
commit7937c6c57e0da7bffa7b10bac23f230c77523e35
treecc6bbea7149e3cac0b0adffbfae75c1496a1d2c6
parente53f21c761d141bbcbce06e9ddab3b4e0a828f2c
clk: pistachio: Fix PLL rate calculation in integer mode

.recalc_rate callback for the fractional PLL doesn't take operating
mode into account when calculating PLL rate. This results in
the incorrect PLL rates when PLL is operating in integer mode.

Operating mode of fractional PLL is based on the value of the
fractional divider. Currently it assumes that the PLL will always
be configured in fractional mode which may not be
the case. This may result in the wrong output frequency.

Also vco was calculated based on the current operating mode which
makes no sense because .set_rate is setting operating mode. Instead,
vco should be calculated using PLL settings that are about to be set.

Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
Cc: <stable@vger.kernel.org> # 4.1
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Zdenko Pulitika <zdenko.pulitika@imgtec.com>
Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/pistachio/clk-pll.c