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(parent: 49a944a) | patch
AMDGPU: Remove SIFixupVectorISel pass
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 13 Aug 2020 20:17:42 +0000 (16:17 -0400)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Sat, 15 Aug 2020 16:11:51 +0000 (12:11 -0400)
commit79298a506707a2cfcffdd7b0346322e5d90776fc
tree78854405ac2d233b16091f919c567a74d8e54e56tree | snapshot
parent49a944af7f1980b54d8a2be0ef640f5a956bc423commit | diff
AMDGPU: Remove SIFixupVectorISel pass

This was only used for matching the saddr addressing mode of global
instructions, but this was not implemented correctly. The instruction
definitions aren't even correct, and are defined as using a 64-bit
VGPR component. Eliminate this pass to enable correcting the
instruction definitions. A new matching implementation can work in
GlobalISel or relying on DAG divergence information for the base
address.
15 files changed:
llvm/lib/Target/AMDGPU/AMDGPU.h diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp diff | blob | history
llvm/lib/Target/AMDGPU/CMakeLists.txt diff | blob | history
llvm/lib/Target/AMDGPU/SIFixupVectorISel.cpp [deleted file] blob | history
llvm/test/CodeGen/AMDGPU/disable_form_clauses.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/ds_write2.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/ds_write2st64.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/global-load-store-atomics.mir [deleted file] blob | history
llvm/test/CodeGen/AMDGPU/global-saddr.ll [deleted file] blob | history
llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-saddr.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/madak.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/memory-legalizer-store.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/memory_clause.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll diff | blob | history
Domain: System / Toolchain;