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drm/amdgpu: Fix GART page table s-bit
authorOak Zeng <Oak.Zeng@amd.com>
Sat, 23 Jan 2021 03:51:39 +0000 (21:51 -0600)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 24 Mar 2021 02:59:02 +0000 (22:59 -0400)
commit79194dacb26a1b31c6d3259144c371795612ce75
tree5da30251cd6c5aaf9eabf05f58d284f8b140dcd4tree | snapshot
parentf4ec3e5039e58b85aab486af6a9c3e5d60cf8be0commit | diff
drm/amdgpu: Fix GART page table s-bit

For the new 2-level GART table, the last PDE0 points
to PTB. Since PTB is in vram and right now we are
runing under s=0 mode (vram is treated as FB carveout),
so the s bit of this PDE0 should be set to 0.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c diff | blob | history
Domain: System / Kernel;