[RISCV] Add explicit types to some XTHead isel patterns to reduce RISCVGenDAGISel...
authorCraig Topper <craig.topper@sifive.com>
Sat, 25 Feb 2023 08:40:09 +0000 (00:40 -0800)
committerCraig Topper <craig.topper@sifive.com>
Sat, 25 Feb 2023 08:40:13 +0000 (00:40 -0800)
commit7910ed1d56c349b76c82d5ebe2f2590770955ff5
treed8634f69624c12e73a4317cba984b89fef11dce5
parentf07bb0012e76495d50b34fe50fe7d41a70c8685b
[RISCV] Add explicit types to some XTHead isel patterns to reduce RISCVGenDAGISel.inc size.

HWMode expansion of GPR can create patterns with i32 types with
Subtarget->is64Bit() or i64 types with !Subtarget->is64Bit().
These patterns will never match. They just waste space in the table.

By adding explicit i32 or i64 to patterns that only apply to RV32
or RV64 we can filter these patterns.
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td