[AArch64][BFloat] add BFloat instruction support for AArch64
authorTies Stuij <ties.stuij@arm.com>
Wed, 27 May 2020 14:27:47 +0000 (15:27 +0100)
committerTies Stuij <ties.stuij@arm.com>
Wed, 27 May 2020 14:36:54 +0000 (15:36 +0100)
commit78bd0c0e5e8fbbfbb9f827bdd1f83f91ed3437fa
tree27b263d1c307a8382e942d6d384f03b27eeff1c4
parent4408eeed0ff191304121c11168aa1db861cccb97
[AArch64][BFloat] add BFloat instruction support for AArch64

Summary:
Add support for lowering various BFloat related SelDAG nodes:
- load/store (ldrh/strh)
- concat
- dup/duplane
- bitconvert/bitcast
- insert_subvector/insert_subreg

This patch is part of a series implementing the Bfloat16 extension of the
Armv8.6-a architecture, as detailed here:

https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a

The bfloat type, and its properties are specified in the Arm Architecture
Reference Manual:

https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile

Reviewers: ab, t.p.northover, john.brawn, fpetrogalli, sdesmalen, LukeGeeson

Reviewed By: fpetrogalli

Subscribers: LukeGeeson, pbarrio, kristof.beyls, hiraditya, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D79712
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/CodeGen/AArch64/bf16-vector-bitcast.ll [new file with mode: 0644]
llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll [new file with mode: 0644]
llvm/test/CodeGen/AArch64/bf16.ll [new file with mode: 0644]