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[ARM] Use ProcResGroup in Cortex-M7 scheduling model
authorDavid Penry <david.penry@arm.com>
Mon, 19 Apr 2021 20:23:05 +0000 (21:23 +0100)
committerDavid Green <david.green@arm.com>
Mon, 19 Apr 2021 20:23:05 +0000 (21:23 +0100)
commit78a871abf7018f4a288b773c9c89f99cd5c66b9c
tree7f65888f3db81d6c5aa0d32cf46c5fc8d495c7f8tree | snapshot
parent3c54762226ed9bcb84dfdef9f8e6e6a2c6a971a0commit | diff
[ARM] Use ProcResGroup in Cortex-M7 scheduling model

Used to model structural hazards on FP issue, where some
instructions take up 2 issue slots and others one as well
as similar structural hazards on load issue, where some
instructions take up two load lanes and others one.

Differential Revision: https://reviews.llvm.org/D98977
llvm/lib/Target/ARM/ARMScheduleM7.td diff | blob | history
llvm/test/CodeGen/ARM/cortex-m7-wideops.mir [new file with mode: 0644] blob
llvm/test/tools/llvm-mca/ARM/m7-fp.s diff | blob | history
llvm/test/tools/llvm-mca/ARM/m7-int.s diff | blob | history
llvm/test/tools/llvm-mca/ARM/m7-negative-readadvance.s diff | blob | history
Domain: System / Toolchain;