[RISCV] Change how we isel (add X, [-4096, -2049]) or (add X, [2048,4095]).
authorCraig Topper <craig.topper@sifive.com>
Fri, 24 Jun 2022 15:21:05 +0000 (08:21 -0700)
committerCraig Topper <craig.topper@sifive.com>
Fri, 24 Jun 2022 15:31:52 +0000 (08:31 -0700)
commit78a31bb96961b30222f96d45b589bad7bc957cb4
tree1071f534df73d3fba7aa2f41012021560d9ed712
parent7736ce1c56c77290cb3ce72ece8e4025fb9e2b22
[RISCV] Change how we isel (add X, [-4096, -2049]) or (add X, [2048,4095]).

We currently split the immediate almost equally between two addis.
If the immediate is odd, it won't be split exactly equal.

This patch instead gives one addi an immediate of 2047 or -2048 and the
other getsthe remainder. If the original immediate is near -2049 or 2048,
this might allow the use of c.addi for the addi that receives the
smaller immediate.

Reviewed By: asb, luismarques

Differential Revision: https://reviews.llvm.org/D128500
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/add-imm.ll
llvm/test/CodeGen/RISCV/addimm-mulimm.ll
llvm/test/CodeGen/RISCV/xaluo.ll