RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w
authorPhilipp Tomsich <philipp.tomsich@vrull.eu>
Wed, 14 Sep 2022 12:16:27 +0000 (14:16 +0200)
committerPhilipp Tomsich <philipp.tomsich@vrull.eu>
Fri, 18 Nov 2022 20:15:24 +0000 (21:15 +0100)
commit787ac95917a666b3d186e2d5afec07ee5b75c6df
tree226dc225e6f03496f02c9783675e857eb0f0bb5f
parent30c2d8df173a6f3ca145cda9f9e261616fca8467
RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w

gcc/ChangeLog:

* config/riscv/bitmanip.md: Handle corner-cases for combine
when chaining slli(.uw)? + addw
* config/riscv/riscv-protos.h (riscv_shamt_matches_mask_p):
Define prototype.
* config/riscv/riscv.cc (riscv_shamt_matches_mask_p):
Helper for evaluating the relationship between two operands.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zba-shNadd-04.c: New test.
gcc/config/riscv/bitmanip.md
gcc/config/riscv/riscv-protos.h
gcc/config/riscv/riscv.cc
gcc/testsuite/gcc.target/riscv/zba-shNadd-04.c [new file with mode: 0644]