intel/isl: Use uint64_t for computed byte offsets
authorJason Ekstrand <jason@jlekstrand.net>
Wed, 7 Jul 2021 16:28:05 +0000 (11:28 -0500)
committerJason Ekstrand <jason@jlekstrand.net>
Tue, 17 Aug 2021 14:36:13 +0000 (09:36 -0500)
commit782f75cb526e44f24a5fb38278167c4c4e00675a
tree14f15dc835a6a99737e329d4a0afe11f1919ee86
parenteb7c28bf24366ae3c30c3a03cbe69747cde49b28
intel/isl: Use uint64_t for computed byte offsets

This is mostly a bit of future-proofing.  We never end up with offsets
that don't fit in 32 bits today because, thanks to driver limitations
caused by relocations, we don't allocate buffers bigger than 2GB today.
However, if we ever did, it's possible to create a surface on modern
platforms that consumes more than 4GB and we would end up with wrapping
in our offset calculations.

Acked-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11765>
12 files changed:
src/gallium/drivers/crocus/crocus_blt.c
src/gallium/drivers/crocus/crocus_state.c
src/gallium/drivers/iris/iris_state.c
src/intel/blorp/blorp_blit.c
src/intel/blorp/blorp_clear.c
src/intel/blorp/blorp_genX_exec.h
src/intel/isl/isl.c
src/intel/isl/isl.h
src/intel/vulkan/anv_image.c
src/intel/vulkan/genX_cmd_buffer.c
src/mesa/drivers/dri/i965/brw_blit.c
src/mesa/drivers/dri/i965/brw_misc_state.c