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(parent: 4fd771e) | patch
drm/amd/display: fix incorrect CM/TF programming sequence in dwb
authorRoy Chan <roy.chan@amd.com>
Mon, 19 Jul 2021 23:00:22 +0000 (19:00 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 9 Aug 2021 19:43:10 +0000 (15:43 -0400)
commit781e1e23131cce56fb557e6ec2260480a6bd08cc
tree51e4a3df9548972334f59113ff48a96ded96af83tree | snapshot
parent4fd771ea441ed98191e8e2c2c1d47e4dc7a0b96acommit | diff
drm/amd/display: fix incorrect CM/TF programming sequence in dwb

[How]
the programming sequeune was for old asic.
the correct programming sequeunce should be similar to the one
used in mpc. the fix is copied from the mpc programming sequeunce.

Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: Roy Chan <roy.chan@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb_cm.c diff | blob | history
Domain: System / Kernel;