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BR 993895: Support zero-operand floating-point insn
authorH. Peter Anvin <hpa@zytor.com>
Thu, 15 Nov 2007 22:38:19 +0000 (14:38 -0800)
committerH. Peter Anvin <hpa@zytor.com>
Thu, 15 Nov 2007 22:38:19 +0000 (14:38 -0800)
commit7812644665f652830fe618716eab4d7e8993af87
treed05f4043ef6289f9e6c79d966df9b0ba474d8575tree | snapshot
parent428fd671ec9d10095ce3a52c7b50276a63f377aecommit | diff
BR 993895: Support zero-operand floating-point insn

Support the zero-operand form of floating-point instructions.  Note
that in most cases, the form generated is actually the "popping" form,
e.g. "FADD" becomes "FADDP st0,st1".  This is in accordance with the
Intel documentation.  "FADDP" is also supported.
insns.dat diff | blob | history
test/fpu.asm [new file with mode: 0644] blob
Domain: System / Toolchain;