intel/compiler: Delete all the A64 atomic variants for type sizes
authorKenneth Graunke <kenneth@whitecape.org>
Tue, 10 Jan 2023 00:44:26 +0000 (16:44 -0800)
committerMarge Bot <emma+marge@anholt.net>
Thu, 19 Jan 2023 08:42:22 +0000 (08:42 +0000)
commit780f3e2e6b6ce2ffd1bb8b6daeeb40244727edd5
tree141dd3e29320052130f57b80bdd36b7c0fa00433
parent03ddde12308dde0a2bcfd5a774e5ec067f7b1d65
intel/compiler: Delete all the A64 atomic variants for type sizes

These are handled identically in almost all cases.  There is one place
in the legacy surface lowering that was obtaining the bitsize from the
opcode, but the LSC-based lowering uses (type_sz(inst->dst.type) * 8)
for that and works just fine.  If we just do that in the legacy lowering
too, then we don't need this plethora of opcodes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20604>
src/intel/compiler/brw_eu_defines.h
src/intel/compiler/brw_fs.cpp
src/intel/compiler/brw_fs.h
src/intel/compiler/brw_fs_nir.cpp
src/intel/compiler/brw_lower_logical_sends.cpp
src/intel/compiler/brw_shader.cpp