author | Chenbing Zheng <Chenbing.Zheng@streamcomputing.com> | |
Wed, 30 Mar 2022 01:50:28 +0000 (09:50 +0800) | ||
committer | Chenbing Zheng <Chenbing.Zheng@streamcomputing.com> | |
Wed, 30 Mar 2022 01:50:28 +0000 (09:50 +0800) | ||
commit | 780eb9f5864ff71afa8e2684c2aa2bcdb9bdfad7 | |
tree | 6b56a5be1e0ff172e5fa42d5e52fde8bcad78ef2 | tree | snapshot |
parent | b5783307543d6379d267f8a90c56a75f9e456395 | commit | diff |
llvm/test/CodeGen/RISCV/bitreverse-shift.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/X86/combine-bitreverse.ll | diff | blob | history |