[RISCV] Implement assembler support for XVentanaCondOps
authorPhilip Reames <preames@rivosinc.com>
Mon, 14 Nov 2022 16:29:55 +0000 (08:29 -0800)
committerPhilip Reames <listmail@philipreames.com>
Mon, 14 Nov 2022 17:01:54 +0000 (09:01 -0800)
commit780c53984449e14f50e2418de993bbf560f54bfc
tree81501804061b73172173dcbbf3558abe297ef9c0
parent4f729d5a7056bbb59621c1332598db924c2f1fd6
[RISCV] Implement assembler support for XVentanaCondOps

This change provides an implementation of the XVentanaCondOps vendor extension. This extension is defined in version 1.0.0 of the VTx-family custom instructions specification (https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf) by Ventana Micro Systems.

In addition to the technical contribution, this change is intended to be a test case for our vendor extension policy.

Once this lands, I plan to use this extension to prototype selection lowering to conditional moves. There's an RVI proposal in flight, and the expectation is that lowering to these and the new RVI instructions is likely to be substantially similar.

Differential Revision: https://reviews.llvm.org/D137350
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td [new file with mode: 0644]
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/XVentanaCondOps-valid.s [new file with mode: 0644]