RISC-V: KVM: Implement guest external interrupt line management
authorAnup Patel <apatel@ventanamicro.com>
Thu, 15 Jun 2023 07:33:44 +0000 (13:03 +0530)
committerAnup Patel <anup@brainfault.org>
Sun, 18 Jun 2023 15:54:33 +0000 (21:24 +0530)
commit77cf33c17154b7f8151429f6ba32049afc49f9c3
tree2b649f96f432bc4513c4667618b414f67af88f02
parent95c99104cb42bea5a0874c362f284ae4b91289dd
RISC-V: KVM: Implement guest external interrupt line management

The RISC-V host will have one guest external interrupt line for each
VS-level IMSICs associated with a HART. The guest external interrupt
lines are per-HART resources and hypervisor can use HGEIE, HGEIP, and
HIE CSRs to manage these guest external interrupt lines.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/asm/kvm_aia.h
arch/riscv/kvm/aia.c
arch/riscv/kvm/main.c
arch/riscv/kvm/vcpu.c