projects / platform / kernel / linux-starfive.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: c31b2af) | patch
soc: sifive: ccache: Add StarFive JH71x0 support
authorEmil Renner Berthing <kernel@esmil.dk>
Tue, 5 Apr 2022 22:38:05 +0000 (00:38 +0200)
committerŁukasz Stelmach <l.stelmach@samsung.com>
Thu, 9 Feb 2023 18:48:02 +0000 (19:48 +0100)
commit77a58e11b4855b7ef724bc103d5f6666c97fe68d
treef7a9981b67092d5842593d17b2986d69044cba54tree | snapshot
parentc31b2af9d111e1f25edd1684eda9f957b1b5cd71commit | diff
soc: sifive: ccache: Add StarFive JH71x0 support

This adds support for the StarFive JH7100 and JH7110 SoCs which also
feature this SiFive cache controller.

Unfortunately the interrupt for uncorrected data is broken on the JH7100
and fires continuously, so add a quirk to not register a handler for it.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
arch/riscv/Kconfig.socs diff | blob | history
drivers/soc/Makefile diff | blob | history
drivers/soc/sifive/Kconfig diff | blob | history
drivers/soc/sifive/sifive_ccache.c diff | blob | history
Domain: System / Kernel;