ARM: 8862/1: errata: 814220-B-Cache maintenance by set/way operations can execute...
authorBenjamin Gaignard <benjamin.gaignard@linaro.org>
Tue, 21 May 2019 09:17:39 +0000 (10:17 +0100)
committerRussell King <rmk+kernel@armlinux.org.uk>
Fri, 21 Jun 2019 08:06:06 +0000 (09:06 +0100)
commit779eb41ccb2e8cc91b63ad5172dfaadcf663f1fa
tree92ea74f3a895ea73546c2bd85e7b5009840c7e55
parente6c4375f7c9293ffa65469d16f8ebd2586cb03f2
ARM: 8862/1: errata: 814220-B-Cache maintenance by set/way operations can execute out of order

The v7 ARM states that all cache and branch predictor maintenance operations
that do not specify an address execute, relative to each other, in program
order. However, because of this erratum, an L2 set/way cache maintenance
operation can overtake an L1 set/way cache maintenance operation, this would
cause the data corruption.

This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.

This patch is the SW workaround by adding a DSB before changing cache levels as
the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation.

Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
arch/arm/Kconfig
arch/arm/mm/cache-v7.S