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arm64: dts: renesas: r8a77970: Add secondary CA53 CPU core
authorGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 9 May 2018 15:23:22 +0000 (17:23 +0200)
committerSimon Horman <horms+renesas@verge.net.au>
Wed, 16 May 2018 08:47:12 +0000 (10:47 +0200)
commit77899dd2c094fc99413e18264384cc428c23cd23
tree5357a8ab39e433946a2c87266a9591de8f5179ectree | snapshot
parentaa7a6365d03aacd4714ae62630f0262cac82a478commit | diff
arm64: dts: renesas: r8a77970: Add secondary CA53 CPU core

Add a device node for the second Cortex-A53 CPU core on the Renesas
R-Car V3M (r8a77970) SoC, and adjust the interrupt delivery masks for
ARM Generic Interrupt Controller and Architectured Timer.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm64/boot/dts/renesas/r8a77970.dtsi diff | blob | history
Domain: System / Kernel;