spi: atmel,quadspi: Define sama7g5 QSPI
authorTudor Ambarus <tudor.ambarus@microchip.com>
Thu, 9 Dec 2021 12:29:39 +0000 (14:29 +0200)
committerMark Brown <broonie@kernel.org>
Wed, 15 Dec 2021 22:16:55 +0000 (22:16 +0000)
commit77850bda360dd9b389d5064c64b79467d613c3d6
tree6be26f21776d6252ff0d279711783075d05f5882
parent001a41d2a7061694fa31accdbc2013bb5c5d83b5
spi: atmel,quadspi: Define sama7g5 QSPI

sama7g5 embedds 2 instances of the QSPI controller:
1/ One Octal Serial Peripheral Interface (QSPI0) Supporting up to
   200 MHz DDR. Octal, TwinQuad, HyperFlash and OctaFlash Protocols
   Supported
2/ One Quad Serial Peripheral Interface (QSPI1) Supporting Up to
   90 MHz DDR/133 MHz SDR

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211209122939.339810-3-tudor.ambarus@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Documentation/devicetree/bindings/spi/atmel,quadspi.yaml