[X86] Remove patterns for shift/rotate with immediate 1 and optimize during MC lowering
authorShengchen Kan <shengchen.kan@intel.com>
Tue, 16 May 2023 14:30:21 +0000 (22:30 +0800)
committerShengchen Kan <shengchen.kan@intel.com>
Wed, 17 May 2023 11:55:44 +0000 (19:55 +0800)
commit77589e945f0d167bd46ed3218b81c16af1e917ae
tree33df08fcd15906cb6667e4840eb6abae1904c9e7
parent7ce3d9228ff1aa881a7aebd451db36dcf159468a
[X86] Remove patterns for shift/rotate with immediate 1 and optimize during MC lowering

It's first suggested by @craig.topper  in D150068. I think there are at least three pros

1. This can reduce the patterns during ISEL, as a result, reducing the bytes in X86GenDAGISel.inc
2. The patterns for shift/rotate with immediate 1 look quite similar to shift/rotate with immediate 8. So this can be seen as eliminating "duplicate" code.
3. Delay the optimization from imm8 to imm1, so that the previous optimization passes do not need to handle the version of imm1

It improves fast isel code and makes X86DomainReassignment work for shifts by 1, but regressed global isel, though no one should care.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D150107
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrShiftRotate.td
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir
llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir
llvm/test/CodeGen/X86/fast-isel-shift.ll
llvm/test/CodeGen/X86/gpr-to-mask.ll
llvm/test/CodeGen/X86/is_fpclass.ll