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author	Qihan Cai <qcai8733@uni.sydney.edu.au>
	Fri, 12 May 2023 08:29:30 +0000 (18:29 +1000)
committer	Qihan Cai <qcai8733@uni.sydney.edu.au>
	Fri, 12 May 2023 08:31:35 +0000 (18:31 +1000)
commit	773b0aaa49170a97b4de7968c4b6dbc7673aba23
tree	b1462b500ead68cf1a295bed71a996769ea26c4f	tree \| snapshot
parent	e6112b6108796f62c30e222804dbf44120e438d2	commit \| diff

[RISCV][CodeGen] Support Zhinx and Zhinxmin

This patch was split from D122918.

Co-Author: @liaolucy @sunshaoce

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D149811

36 files changed:

llvm/docs/RISCVUsage.rst		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVFeatures.td		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVISelLowering.cpp		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVSubtarget.h		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-arith-strict.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-arith.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-br-fcmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-convert-strict.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-convert.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-fcmp-strict.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-fcmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-frem.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-imm.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-isnan.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-mem.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-round-conv-sat.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-round-conv.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-select-fcmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/half-select-icmp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64zfh-half-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/zfh-half-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/zfh-imm.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/zfhmin-imm.ll		diff \| blob \| history

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