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(parent: 87273b7) | patch
drm/i915: Perform Sandybridge BSD tail write under the forcewake
authorChris Wilson <chris@chris-wilson.co.uk>
Thu, 30 Jun 2016 14:33:45 +0000 (15:33 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Thu, 30 Jun 2016 14:42:34 +0000 (15:42 +0100)
commit76f8421f2a67cdecd616705b7a0c3750d6d42c05
treeef1c0b47412308e20c7e839ffef4e199b95b965atree | snapshot
parent87273b7110a031c7b258f8c05efcd88194f79fe8commit | diff
drm/i915: Perform Sandybridge BSD tail write under the forcewake

Since we have a sequence of register reads and writes, we can reduce the
latency of starting the BSD ring by performing all the mmio operations
under the same forcewake wakeref.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1467297225-21379-62-git-send-email-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/i915_drv.h diff | blob | history
drivers/gpu/drm/i915/intel_ringbuffer.c diff | blob | history
Domain: System / Kernel;