[ARM] VCVTT instruction selection
authorDavid Green <david.green@arm.com>
Fri, 26 Jun 2020 07:02:26 +0000 (08:02 +0100)
committerDavid Green <david.green@arm.com>
Fri, 26 Jun 2020 07:58:55 +0000 (08:58 +0100)
commit76e0e1a55d1ccecebbd98fb1fa5c7ab5a4f013cc
tree1160da0f8476daf9a036c7118b9e7e0d40d1c93e
parent48f1d4fcd27ca8aefc1cbe61b133a677f5bdcb93
[ARM] VCVTT instruction selection

We current extract and convert from a top lane of a f16 vector using a
VMOVX;VCVTB pair. We can simplify that to use a single VCVTT. The
pattern is mostly copied from a vector extract pattern, but produces a
VCVTTHS f32 directly.

This had to move some code around so that ARMInstrVFP had access to the
required pattern frags that were previously part of ARMInstrNEON.

Differential Revision: https://reviews.llvm.org/D81556
llvm/lib/Target/ARM/ARMInstrInfo.td
llvm/lib/Target/ARM/ARMInstrNEON.td
llvm/lib/Target/ARM/ARMInstrVFP.td
llvm/test/CodeGen/ARM/fp16-insert-extract.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
llvm/test/CodeGen/Thumb2/mve-div-expand.ll
llvm/test/CodeGen/Thumb2/mve-fmath.ll
llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
llvm/test/CodeGen/Thumb2/mve-vcvt16.ll