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arm: dts: exynos5422: change BPLL clock to 933MHz
authorInki Dae <inki.dae@samsung.com>
Fri, 23 Nov 2018 08:30:37 +0000 (17:30 +0900)
committerJunghoon Kim <jhoon20.kim@samsung.com>
Thu, 14 Feb 2019 05:57:44 +0000 (14:57 +0900)
commit76ddac6c701df33a3a8e0c8f988761557ef1e162
tree61b0a9a211ad089fd94a7561b3c37754656f7c38tree | snapshot
parentafe73d9956904d7cee29f1c26a00b8303f607ecbcommit | diff
arm: dts: exynos5422: change BPLL clock to 933MHz

This patch changes BPLL clock to 933MHz for DREX controller
can use maximum speed.

Change-Id: Ia06079c32ad532cb8a53d9dcae6a7fbacf80895a
Signed-off-by: Inki Dae <inki.dae@samsung.com>
arch/arm/boot/dts/exynos5422-odroid-core.dtsi diff | blob | history
Domain: System / Kernel;