net: ethernet: mtk_eth_soc: remove incorrect PLL configuration
authorRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Sat, 22 Jul 2023 20:32:49 +0000 (21:32 +0100)
committerPaolo Abeni <pabeni@redhat.com>
Tue, 25 Jul 2023 13:02:03 +0000 (15:02 +0200)
commit76a4cb755cf911ad5acdb82f7228a9e22addf52b
tree48f2bb0a406cc3247511f996ee086001c92fa845
parentec87f05402f592d27507e1aa6b2fd21c486f2cc0
net: ethernet: mtk_eth_soc: remove incorrect PLL configuration

MT7623 GMAC0 attempts to configure the system clocking according to the
required speed in the .mac_config callback for non-SGMII, non-baseX and
non-TRGMII modes.

state->speed setting has never been reliable in the .mac_config
callback - there are cases where this is not the link speed,
particularly via ethtool paths, so this has always been unreliable (as
detailed in phylink's documentation.)

There is the additional issue that mtk_gmac0_rgmii_adjust() will only
be called if state->interface changes, which means it only configures
the system clocking on the very first .mac_config call, which will be
made when the network device is first brought up before any link is
established.

Essentially, this code is incredibly buggy, and probably never worked.

Moreover, checking the in-kernel DT files, it seems no platform makes
use of this code path.

Therefore, let's remove it, and disable interface modes for port 0 that
are not SGMII, 1000base-X, 2500base-X or TRGMII on the MT7623.

Reviewed-by: Daniel Golle <daniel@makrotopia.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
drivers/net/ethernet/mediatek/mtk_eth_soc.c
drivers/net/ethernet/mediatek/mtk_eth_soc.h