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(parent: b4e64a7) | patch
[x86] add folds for FP logic with vector zeros
authorSanjay Patel <spatel@rotateright.com>
Tue, 27 Sep 2016 22:28:13 +0000 (22:28 +0000)
committerSanjay Patel <spatel@rotateright.com>
Tue, 27 Sep 2016 22:28:13 +0000 (22:28 +0000)
commit764ae8bd72aac2cf77cb24d0e1c1136c3179e09b
treee9c26115264abdc80b4238a50536ec7228e7c2bctree | snapshot
parentb4e64a77d3f7c410e0548b659e61ce0d1ca54f08commit | diff
[x86] add folds for FP logic with vector zeros

The 'or' case shows up in copysign. The copysign code also had
redundant checking for a scalar zero operand with 'and', so I
removed that.

I'm not sure how to test vector 'and', 'andn', and 'xor' yet,
but it seems better to just include all of the logic ops since
we're fixing 'or' anyway.

llvm-svn: 282546
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/X86/copysign-constant-magnitude.ll diff | blob | history
Domain: System / Toolchain;