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[AMDGPU] Skip generating cache invalidating instructions on AMDPAL
authorPiotr Sobczak <Piotr.Sobczak@amd.com>
Fri, 24 Apr 2020 07:56:41 +0000 (09:56 +0200)
committerPiotr Sobczak <Piotr.Sobczak@amd.com>
Fri, 24 Apr 2020 11:53:44 +0000 (13:53 +0200)
commit7631af3af2799cdc8963d5c1d8f4261f6442b3ea
tree5b3b76af3d105f1044f315dfff1b489c4003d643tree | snapshot
parent7aaff8fd2da2812a2b3cbc8a41af29774b10a7d6commit | diff
[AMDGPU] Skip generating cache invalidating instructions on AMDPAL

Summary:
Frontend guarantees that coherent accesses have
corresponding cache policy bits set (glc, dlc).
Therefore there is no need for extra instructions
that invalidate cache.

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78800
llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/memory-legalizer-amdpal.ll diff | blob | history
Domain: System / Toolchain;