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(parent: dbdc13a) | patch
target-ppc/fpu_helper: fix FPSCR_FX bit shift operation
authorMadhavan Srinivasan <maddy@linux.vnet.ibm.com>
Fri, 20 Nov 2015 11:31:48 +0000 (17:01 +0530)
committerDavid Gibson <david@gibson.dropbear.id.au>
Mon, 30 Nov 2015 08:39:01 +0000 (19:39 +1100)
commit7624789234cd63b671bce1b49b93b0b1c00ea407
tree0b77cd9ab7c23b95eca2202e03215b8c13b5641atree | snapshot
parentdbdc13a1ac0bfaa9a2d7069e9e6509721ed795eecommit | diff
target-ppc/fpu_helper: fix FPSCR_FX bit shift operation

Currently in TCG mode, updating floating exception
summary bit (FPSCR_FX) in fpscr also updates
the upper 32bits of fpscr with all 1s.
Modify the bit shift operation statement to use
1ULL instead.

Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
target-ppc/fpu_helper.c diff | blob | history
Domain: SDK / Emulator;