drm/i915/psr: Prevent PSR exit when a non-pipe related register is written
authorosé Roberto de Souza <jose.souza@intel.com>
Wed, 25 Apr 2018 21:23:31 +0000 (14:23 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 26 Apr 2018 22:35:06 +0000 (15:35 -0700)
commit75cbec033c08f6d41c4775784f66ab860d02a6b5
tree53d9b77ad52943262ca9a3bc42408d8879cd9b1d
parent935dff1a218c2162aad8f0e681cbb5d601742412
drm/i915/psr: Prevent PSR exit when a non-pipe related register is written

Any write in any display register was causing HW to exit PSR,
masking it to allow more power savings. Writes to pipe related
registers will still cause HW to exit PSR.
This is already masked for PSR2.

It also do not break the Display WA #0884, writes to CURSURFLIVE
are still causing hardware to exit PSR. This was tested in CNL machine
by triggering a write to CURSURFLIVE when a debugfs was read by user.

Bspec: 7721 and 8042

v4: Checked that it do not breaks WA #0884 and added this information
to the commit message.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180425212334.21109-1-jose.souza@intel.com
drivers/gpu/drm/i915/intel_psr.c