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(parent: 73e770f) | patch
soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()
authorYang Yingliang <yangyingliang@huawei.com>
Tue, 18 Oct 2022 02:31:48 +0000 (10:31 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 9 Nov 2022 22:01:31 +0000 (22:01 +0000)
commit756344e7cb1afbb87da8705c20384dddd0dea233
tree5cf47a2399cd9df46d3a1981731226f490cbc1f1tree | snapshot
parent73e770f085023da327dc9ffeb6cd96b0bb22d97ecommit | diff
soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()

Add missing free_irq() before return error from sifive_ccache_init().

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
drivers/soc/sifive/sifive_ccache.c diff | blob | history
Domain: System / Kernel;