review.tizen.org Git - platform/upstream/llvm.git/commit

projects / platform / upstream / llvm.git / commit

author	4vtomat <brandon.wu@sifive.com>
	Wed, 12 Apr 2023 02:49:14 +0000 (19:49 -0700)
committer	4vtomat <brandon.wu@sifive.com>
	Tue, 2 May 2023 05:30:08 +0000 (22:30 -0700)
commit	74c1fa60b5f5c1d079e08a2e409a649a26da41d1
tree	62dd80f8d60450531cc13d018e1a3d0fb93b00b7	tree \| snapshot
parent	4e4db6f6c6ce13855d03f1e7a00296e49fed0765	commit \| diff

[RISCV] Add Smaia and Ssaia extensions support

This patch implements 1.0-RC3:
https://github.com/riscv/riscv-aia/releases/download/1.0-RC3/riscv-interrupts-1.0-RC3.pdf

Differential Revision: https://reviews.llvm.org/D148066

15 files changed:

clang/test/Preprocessor/riscv-target-features.c		diff \| blob \| history
llvm/docs/RISCVUsage.rst		diff \| blob \| history
llvm/lib/Support/RISCVISAInfo.cpp		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVFeatures.td		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVSystemOperands.td		diff \| blob \| history
llvm/test/CodeGen/RISCV/attributes.ll		diff \| blob \| history
llvm/test/MC/RISCV/attribute-arch.s		diff \| blob \| history
llvm/test/MC/RISCV/hypervisor-csr-names.s		diff \| blob \| history
llvm/test/MC/RISCV/machine-csr-names.s		diff \| blob \| history
llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s		diff \| blob \| history
llvm/test/MC/RISCV/rv32-machine-csr-names.s		diff \| blob \| history
llvm/test/MC/RISCV/rv32-only-csr-names.s		diff \| blob \| history
llvm/test/MC/RISCV/rv32-supervisor-csr-names.s		diff \| blob \| history
llvm/test/MC/RISCV/rvi-aliases-valid.s		diff \| blob \| history
llvm/test/MC/RISCV/supervisor-csr-names.s		diff \| blob \| history

Domain: System / Toolchain;

RSS Atom