clk:starfive:Set PLL2 frequency when clock tree registering
authorxingyu.wu <xingyu.wu@starfivetech.com>
Fri, 15 Jul 2022 08:51:21 +0000 (16:51 +0800)
committerxingyu.wu <xingyu.wu@starfivetech.com>
Wed, 20 Jul 2022 08:48:13 +0000 (16:48 +0800)
commit749c585f1c93bdb9cd03d9872e14e9110f31fb70
tree6eab4fbd1cfa9b47ce04e439dfcd021455986489
parent7ab7898ae6ccd44551acd1cde1cc7a6b5039f6b4
clk:starfive:Set PLL2 frequency when clock tree registering

In the file drivers/clk/starfive/clk-starfive-jh7110-pll.h,
If set PLL2_DEFAULT_FREQ NULL of 0 , then PLL2 frequency is original.
If set PLL2_DEFAULT_FREQ one of 'starfive_pll2_freq_value', then PLL2
frequency will be set the new rate during clock tree registering.

Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
drivers/clk/starfive/clk-starfive-jh7110-pll.c
drivers/clk/starfive/clk-starfive-jh7110-pll.h