ARC: [axs101] Tweak DDR port aperture mappings for performance
authorVineet Gupta <vgupta@synopsys.com>
Tue, 27 May 2014 13:57:37 +0000 (19:27 +0530)
committerVineet Gupta <vgupta@synopsys.com>
Fri, 19 Jun 2015 12:39:31 +0000 (18:09 +0530)
commit749aa0e11a7f551d1133b391cf8a160718d7ca50
tree074e43f5189033ab46bc2393e0cab479dc10b76e
parent8d0d56ba24d8d0b04bc9d9a7fbd1796d8966159f
ARC: [axs101] Tweak DDR port aperture mappings for performance

Route all MB originated traffic to DDR Port 1 and keep Port 0 for CPU
traffic only

Basic system parameters
--------------------------------------------------------------------------------------
        Host                 OS Description  Mhz  tlb   cache  mem   scal
                                                     pages  line   par   load
                                                          bytes
----------------- ------------- --------------------------------------- ---- ----- ----- ------ ----
axs101-sd-2-new-f Linux 3.13.0+ axs101-sd-2-new-fw-old-img-rerun     739   8    32 1.1100    1
axs101-sd-3-arc-3 Linux 3.13.9+ axs101-sd-3-arc-3.13-tip-regression  735   8    32 1.1000    1
axs101-sd-9-diffe Linux 3.13.11 axs101-sd-9-different-tweak          740   8    32 1.0000    1

Processor, Processes - times in microseconds - smaller is better
------------------------------------------------------------------------------
Host                 OS  Mhz null null      open slct sig  sig  fork exec sh
                             call  I/O stat clos TCP  inst hndl proc proc proc
--------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
axs101-sd Linux 3.13.0+  739 0.50 0.88 5.38 14.6 34.1 0.92 5.18 2135 6555 12.K
axs101-sd Linux 3.13.9+  735 0.50 0.90 5.89 19.2 81.4 0.94 4.08 2560 8559 15.K
axs101-sd Linux 3.13.11  740 0.50 0.88 4.45 17.8 34.4 0.94 3.25 2052 6493 12.K
                                                 ^^^^                     ^^^^

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
arch/arc/plat-axs10x/axs10x.c