mx25pdk: Set the eSDHC PER clock to 48 MHz
authorBenoît Thébaudeau <benoit@wsystem.com>
Wed, 3 May 2017 09:59:06 +0000 (11:59 +0200)
committerStefano Babic <sbabic@denx.de>
Wed, 31 May 2017 08:14:41 +0000 (10:14 +0200)
commit747778cf69468daa1f35abb932e17032ddfe9c1a
tree941e43aba76e6868955a8a57d4186cbf077f758d
parent3e3aab3379d99f4c955ecca4992ad33ae70e71e4
mx25pdk: Set the eSDHC PER clock to 48 MHz

The maximum SD clock frequency in High Speed mode is 50 MHz. This change
makes it possible to get 48 MHz from the USB PLL (240 MHz / 5 / 1)
instead of the previous 33.25 MHz from the AHB clock (133 MHz / 2 / 2).

Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
board/freescale/mx25pdk/mx25pdk.c