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(parent: b690308) | patch
drm/amdgpu: revise the mode2 reset for vangogh
authorHuang Rui <ray.huang@amd.com>
Wed, 2 Dec 2020 07:28:23 +0000 (15:28 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 14 Jan 2021 04:48:13 +0000 (23:48 -0500)
commit743538838c6a6b368ef58cad9528b15615e4ec33
tree3490e001358ad49c43a4e31630c3eca746392a0dtree | snapshot
parentb6903089a5ab74e8bcae963d5ca60b0005b75c05commit | diff
drm/amdgpu: revise the mode2 reset for vangogh

PCIE MMIO bar needs to be restored firstly after the reset event
triggers. So it's unable to access the registers to wait for response
from SMU. Becasue the value of mmMP1_SMN_C2PMSG_90 is invalid at that
moment.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c diff | blob | history
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c diff | blob | history
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h diff | blob | history
Domain: System / Kernel;