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(parent: b370615) | patch
[SelectionDAG] https://reviews.llvm.org/D48278
authorDiogo N. Sampaio <diogo.sampaio@arm.com>
Fri, 6 Jul 2018 09:42:25 +0000 (09:42 +0000)
committerDiogo N. Sampaio <diogo.sampaio@arm.com>
Fri, 6 Jul 2018 09:42:25 +0000 (09:42 +0000)
commit742bf1a255691f2988c50031c92e1d7cfd913ace
tree30d276dcbe4dcbee35e772d6a8cd1899f9e21219tree | snapshot
parentb3706154514ee4cb432122f7f822ebecee97f688commit | diff
[SelectionDAG] https://reviews.llvm.org/D48278

D48278

Allow to reduce redundant shift masks.
For example:
x1 = x & 0xAB00
x2 = (x >> 8) & 0xAB

can be reduced to:
x1 = x & 0xAB00
x2 = x1 >> 8
It only allows folding when the masks and shift values are constants.

llvm-svn: 336426
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff | blob | history
llvm/test/CodeGen/AArch64/FoldRedundantShiftedMasking.ll [new file with mode: 0644] blob
llvm/test/CodeGen/ARM/FoldRedundantShiftedMasking.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/pr32329.ll diff | blob | history
Domain: System / Toolchain;