[X86] Add -x86-experimental-vector-widening support to reduceVMULWidth and combineMul...
authorCraig Topper <craig.topper@intel.com>
Thu, 15 Nov 2018 18:59:31 +0000 (18:59 +0000)
committerCraig Topper <craig.topper@intel.com>
Thu, 15 Nov 2018 18:59:31 +0000 (18:59 +0000)
commit73bb04ab6ff0efdfc38cc2c9fa176f6ee28700f7
treed8141e832d326fd728e18715cd400d3bb4648794
parentfc3163b67a87e93e8beda976ccd16418ca879284
[X86] Add -x86-experimental-vector-widening support to reduceVMULWidth and combineMulToPMADDWD

In reduceVMULWidth, we no longer need to worry about extending the vector to 128 bits first. Regular widening of extends, muls and shuffles will take care of that for us.

In combineMulToPMADDWD, we can handle v2i32 multiplies and allow the VPMADDWD to be widened to v4i32 during type legalization by adding custom widening like we do have for AVG/ADDUS/SUBUS. I had to modify that code a little to allow different and output VTs.

Differential Revision: https://reviews.llvm.org/D54512

llvm-svn: 346980
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/shrink_vmul-widen.ll