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(parent: b0b07a2) | patch
amd64_edac: Add a fix for Erratum 505
authorBorislav Petkov <borislav.petkov@amd.com>
Mon, 19 Sep 2011 15:34:45 +0000 (17:34 +0200)
committerBorislav Petkov <borislav.petkov@amd.com>
Thu, 6 Oct 2011 10:34:05 +0000 (12:34 +0200)
commit73ba85937b2a07b6401ba0b7ca06a112762de9f7
treef4905768cf9cc469b79e92a3c7cf9dec2c6079b1tree | snapshot
parentb0b07a2bd4fbb6198d4e7142337214eeb77c417acommit | diff
amd64_edac: Add a fix for Erratum 505

When accessing the scrub rate control register (F3x58) on F15h, the DRAM
controller selector (F1x10C[DctCfgSel]) has to point to DCT0 so that the
scrub rate configuration can take effect. See Erratum 505 in the AMD
F15h revision guide for more details.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
drivers/edac/amd64_edac.c diff | blob | history
Domain: System / Uncategorized;