[SelectionDAG][PowerPC][AArch64][X86][ARM] Add chain input and output the ISD::FLT_RO...
authorCraig Topper <craig.topper@intel.com>
Wed, 26 Feb 2020 00:57:42 +0000 (16:57 -0800)
committerCraig Topper <craig.topper@intel.com>
Wed, 26 Feb 2020 00:58:23 +0000 (16:58 -0800)
commit735d27dc4065219478a7d314f835961f8517c658
tree46f22b07a7d867403df5f589c3a53f48f58bac4a
parent28d38a25e963f43cd9f392617ff14ff5cb40a8c6
[SelectionDAG][PowerPC][AArch64][X86][ARM] Add chain input and output the ISD::FLT_ROUNDS_

This node reads the rounding control which means it needs to be ordered properly with operations that change the rounding control. So it needs to be chained to maintain order.

This patch adds a chain input and output to the node and connects it to the chain in SelectionDAGBuilder. I've update all in-tree targets to connect their chain through their lowering code.

Differential Revision: https://reviews.llvm.org/D75132
llvm/include/llvm/CodeGen/ISDOpcodes.h
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/flt-rounds.ll