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(parent: 403da6a) | patch
[MCA] Support in-order CPUs with MicroOpBufferSize=1
authorJay Foad <jay.foad@amd.com>
Tue, 9 Mar 2021 16:12:36 +0000 (16:12 +0000)
committerJay Foad <jay.foad@amd.com>
Thu, 11 Mar 2021 10:12:54 +0000 (10:12 +0000)
commit7340fd68862ccc9c378beef6433e6d627e619bca
treee1fe4385d93dd533e01c06e057967e2c1c81c0detree | snapshot
parent403da6a69abc357066117370a5b80e03594b81a6commit | diff
[MCA] Support in-order CPUs with MicroOpBufferSize=1

Differential Revision: https://reviews.llvm.org/D98356
llvm/lib/MCA/HardwareUnits/RetireControlUnit.cpp diff | blob | history
llvm/test/tools/llvm-mca/AMDGPU/gfx10-add-sequence.s [new file with mode: 0644] blob
llvm/test/tools/llvm-mca/AMDGPU/lit.local.cfg [new file with mode: 0644] blob
Domain: System / Toolchain;