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RISC-V: properly determine hardware caps
authorAndreas Schwab <schwab@suse.de>
Tue, 23 Oct 2018 07:33:47 +0000 (09:33 +0200)
committerPalmer Dabbelt <palmer@sifive.com>
Wed, 31 Oct 2018 19:13:43 +0000 (12:13 -0700)
commit732e8e4130ffccb618390e0f80a884543e61fd61
tree49654d9e8c7afcb00c220a99262f6f3faf7df857tree | snapshot
parentd26c4bbf992463c043fdee4b3e5efa3f08990862commit | diff
RISC-V: properly determine hardware caps

On the Hifive-U platform, cpu 0 is a masked cpu with less capabilities
than the other cpus.  Ignore it for the purpose of determining the
hardware capabilities of the system.

Signed-off-by: Andreas Schwab <schwab@suse.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
arch/riscv/kernel/cpufeature.c diff | blob | history
Domain: System / Kernel;